1. Technical Field
The present invention relates to a semiconductor system, and more particularly, to a semiconductor system including a transmission circuit.
2. Related Art
In general, a semiconductor memory apparatus includes a plurality of data pads to communicate with controllers such as a central processing unit (CPU) and a graphic processor unit (GPU), which are configured to control the semiconductor memory apparatus.
Furthermore, the semiconductor memory apparatus may generate a multi-phase clock signal having multiple phases for an external clock signal, in order to more quickly output data. The semiconductor memory apparatus may achieve high-speed data output by outputting data to the data pads according to the multi-phase clock signal.
The controllers configured to control the semiconductor memory apparatus may receive data, which is outputted from the data pads, in synchronization with a data strobe signal.
With the integration of semiconductor memory apparatuses, a physical distance between the plurality of data pads is gradually decreasing. Accordingly, severe crosstalk may occur between the plurality of data pads or between transmission lines for transmitting data from/to the data pads.
Furthermore, such crosstalk may occur even in channels of controllers communicating with a semiconductor memory apparatus. As the physical distance between data pads of the semiconductor memory apparatus decreases, a distance between the channels of the controllers is also decreasing.
Such crosstalk may be influenced by transition patterns of logic value of data applied to adjacent data pads and transmission lines. More specifically, if logic values of the data applied to the adjacent data pads and the adjacent transmission lines transit at the same time, the crosstalk may increase, and thus data reliability may deteriorate.